1. Field of the Invention
The present invention relates to electrically programmable read only memory (EPROM) devices and, in particular, to a unique contactless 5V-only EPROM array that utilizes cells that rely on source side injection for programming.
2. Discussion of the Prior Art
An electrically programmable read only memory (EPROM) device is a non-volatile memory integrated circuit which is used to store binary data. Power can be removed from an EPROM without loss of data. That is, upon reapplying power, the originally-stored binary data is retained.
In addition to its data retention capability, an EPROM can also be reprogrammed to store new binary data. Reprogramming is accomplished by first exposing the EPROM to an ultra-violet (UV) light source in order to erase the old binary data. A UV-transparent lid on the packaged EPROM chip allows this erasure to occur. Following erasure, the new binary data is written into the EPROM by deactivating the chip select line in order to switch the EPROM's data outputs to inputs. The EPROM address inputs are then set to a starting value, the desired data is connected to the data inputs and the data is written into the data storage register identified by the address inputs. The address inputs are then incremented and the cycle is repeated for each data storage register in the EPROM array.
In an EPROM read operation, the binary data stored in the data storage register identified at the address inputs is connected to the chip's data output buffers. If the EPROM's chip select signal is activated, then the binary data from the selected storage register is provided to the data bus.
An electrically erasable programmable read only memory (EEPROM) is a variation in EPROM design wherein binary data is read, written and erased electrically. A single operation erases the selected data storage register. In the case of a so-called "flash" EPROM, all data storage registers in the memory array are electrically erased in a single operation.
A conventional EPROM cell includes buried N+source and drain regions formed in a P-type silicon substrate and separated by a substrate channel region. A polysilicon floating gate (poly 1) is formed on a dielectric layer, usually silicon dioxide, overlying the channel region. A polysilicon control gate (poly 2) is formed over the poly 1 floating gate and is separated therefrom by insulating material, typically an oxide-nitrideoxide (ONO) composite.
The logic state of the above-described cell, i.e, whether it is storing a "1" or a "0", is determined by the charge on the poly 1 floating gate. When electrons are placed on the floating gate, the threshold voltage required to turn on the cell by applying a potential to the poly 2 control gate is much greater than when no electrons are placed on the floating gate.
U.S. Pat. No. 4,794,565, issued Dec. 27, 1988 to Wu et al, discloses the concept of a source-side injection EPROM cell. The Wu et al cell provides for the improved efficiency of hot electron injection from the source to the floating gate during programming. The Wu et al cell includes the conventional N+ source and drain regions formed in a P-type silicon substrate to define a substrate channel. A poly 2 control gate overlies the channel region and a poly i floating gate, insulated from the control gate and from the source and drain regions, is located beneath the control gate. A weak gate control region, or access transistor, is provided near the source region so that a relatively high channel electric field is created in the region between the weak control gate and the floating gate for promoting hot electron injection from the source to the floating gate when the cell is biased for programming.
Since a low current approach to programming eliminates the need for the external high voltage source usually required for EPROM cells, the high voltage being generated from an internal 5V supply, high speed, 5V only, UV-erasable and flash EPROMs are becoming of greater interest, particularly for use in programmable logic devices. However, only a few 5V EPROM products are presently described in the literature.
Gill et al, "A 5 Volt Contactless Array 256K Bit Flash EEPROM Technology", describe a contactless EPROM cell for a single power supply 5V flash EEPROM. The cell utilizes buried N+ source and drain regions. The oxide between the cell's floating gate and the substrate near the source is 100.ANG. thick for programming the cell via hot-electron injection and for erasing the cell via Fowler-Nordheim tunneling. Because of the low current requirements for programming and erase, the programming voltage Vpp can be generated internally from a 5V supply. A gate oxide near the tunnel window is 250.ANG. thick to improve source junction field plate breakdown voltage. The pass gate, which utilizes a 500.ANG. thick gate oxide, prevents the cell from drawing current even when the floating gate structure is overerased into depletion. The buried N+ source and drain regions of the cell constitute the continuous buried bit lines.
The Gill et al cell, however, requires a very complicated process for fabrication.
Naruke et al, "A New Flash-Erase EEPROM Cell With A Sidewall Select-Gate On Its Source Side", IEDM 1986, describe a flash EPROM cell that also features 5V-only programming. The cell, shown in FIGS. 2A-2C, consists of a triple polysilicon, stacked-gate MOS transistor with a side-wall polysilicon select gate spacer on the source side.
As shown in FIG. 1A, because of the high field, high gate current of the Naruke et al cell at the spacer-to-stack interface when programming, the use of more than 5V on the drain side can be avoided.
FIG. 1B shows the typical operating voltages of the Naruke et al cell in the read mode. Since the cell is free of turn-on, i.e. the access spacer transistor prevents the other cells on the same bit line from being leaky during programming, there is no need for a punch-through implant in the memory cell. This increases the mobility value and, thus, increases the read current. From another point of view, putting 5V on the poly spacer in the read mode inverts the silicon under the spacer, leading to an effective channel length Leff equal to the length of the poly 1 floating gate. This leads to high read current and, thus, small read access time.
FIG. 1C shows typical operating voltages of the Naruke et al cell in the erase mode. Erase occurs through Fowler-Nordheim tunneling across the thin gate oxide (100.ANG.) at the drain edge. As shown in FIG. 1C, the drain of the cell is graded to increase gate induced breakdown voltage.
The Naruke et all cell is a complicated device to manufacture because of the triple-poly process required to fabricate the access transistor spacer. Furthermore, it relies on a T-shaped cell design that utilizes one contact for every two cells, thus consuming valuable die area. In addition, the spacer extends along the entire length of the word line, creating potential fabrication problems relating to spacer resistance and continuity.
Van Houdt et al, "Study of the enhanced hotelectron injection in split-gate transistor structures", a paper presented at ESSDERC 90, Nottingham, Sep. 1990, Session 3C5, disclose a double-poly, split-gate cell structure which, they suggest, can be used in a 5V-only EPROM or flash-EPROM array. However, the Van Houdt et al cell is not disclosed as utilizable in a contactless EPROM array.